In light of the continued uncertain surrounding the COVID-19 situation, the conference will be a virtual event with a duration of 2 days.
|CEST||Tuesday 29 June||Wednesday 30 June|
|09:00 – 12:00||LUTNet Tutorial|
|12:00 – 14:00||Break|
|14:00 – 14:50||Keynote||09:00 – 10:15||Design tools 1|
|14:50 – 15:00||Break||10:15 – 10:35||Break|
|15:00 – 16:00||Applications||10:35 – 12:00||Design tools 2|
|16:00 – 16:20||Break||12:00 – 13:30||Break|
|16:20 – 17:40||Security||13:30 – 15:00||Architecture|
|17:40 – 18:20||Interactive presentations 1||15:00 – 16:00||Interactive presentations 2|
Generating energy-efficient deep neural networks on embedded FPGAs using LUTNet.
The KI-Sprung: LUTNet project was born in 2019 when researchers from OFFIS e.V. and the University of Duisburg-Essen decided to join forces to develop a toolchain for generating energy-efficient deep neural networks on embedded FPGAs. LUTNet received funding from the German BMBF in the KI-Sprung national competition for energy-efficient machine learning. Up to now LUTNets mainly focused on energy-efficient 1D-convolutional neural networks. As a toolchain LUTNet supports Xilinx FPGAs as hardware accelerators for the inference phase. Access to these is transparent to the user and realised via automatically generated hardware-software interfaces. It combines a model-based optimisation approach for low bit-width quantised neural networks with a stream-based bufferless inference pipeline on hardware. This way LUTNet can detect atrial fibrillation in real-world ECG samples with a sensitivity of 92% and a fallout of 12%. A 2000mAh battery can support 2400 hours (100 days) of ecg data analysis.
FPGA Hardware Security in the Cloud – Do service providers know what they are doing?
Abstract: FPGAs are becoming mainstream in cloud datacenters. For instance, all currently refurbished Microsoft datacenters get equipped with FPGA instances. While this is an exciting movement for reconfigurable computing, this movement comes with new hardware security challenges. Traditionally, FPGA systems had been closed to users, and a system integrator had exclusive control over the FPGA configuration and, consequently, the complete system security. However, in a cloud setting, users themselves deploy hardware designs on the FPGAs, which can be used for various attack scenarios ranging from leaking information all the way to damaging the equipment.
This keynote will survey recent security attacks tailored to cloud FPGA settings, and we will look deeper into recent experiments on attacking Amazon AWS F1 instances. We managed to crash about 100 AWS instances to showcase a denial-of-service attack, and we bypassed some of the AWS protection mechanisms, such as clock gating on detecting excessive power consumption. Moreover, we used PUF fingerprinting to reverse engineer scheduling policies. We show that FPGAs can be configured with user circuits that bypass AWS security fences and FPGA vendor design rule checks, but that can demand kilowatts of dynamic power consumption if deployed on a datacenter FPGA.
Most importantly, we reveal mitigation techniques that scan configuration bitstreams for potential malicious circuits, and we show how such mitigation techniques can be embedded into existing FPGA security architectures. We show that the security of FPGA hardware is well manageable in a similar way as known from software systems. However, we will point to open questions in order to stimulate future research and to make FPGAs successful in datacenters in the long term.
Bio: Dirk Koch is a Reader in the Advanced Processor Technologies Group at the University of Manchester. His main research interests include run-time reconfigurable systems based on FPGAs, embedded systems, computer architecture, VLSI and hardware security. Dirk’s group developed techniques and the GoAhead tool for implementing self-adaptive distributed embedded control systems based on FPGAs. Current research projects include database acceleration using FPGAs-based stream processing, HPC and exascale computing and using FPGAs in datacenters. Moreover, his group maintains the FABulous open-source embedded FPGA generation framework, which was used to design chips in TSMC and Skywater processes. Dirk Koch is the author of the book “Partial Reconfiguration on FPGAs” and a co-editor of the book “FPGAs for Software Programmers”.
|Tuesday 29 June|
|09:00-12:00||Generating energy-efficient deep neural networks on embedded FPGAs using
LUTNet, The KI-Sprung
|14:05-14:50||FPGA Hardware Security in the Cloud – Do service providers know what they are doing?, Dirk Koch|
|15:00-16:00||Applications (Chair: Sergio Pertuz)|
|15:00-15:25||Fast Approximation of the Top-k Items in Data Streams Using a Reconfigurable Accelerator, Ali Ebrahim and Jalal Khalifat|
|15:25-15:50||Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases, Johannes Wirth, Jaco Hofmann , Lasse Thostrup, Andreas Koch and Carsten Binnig|
|15:50-15:53||IP: Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU, Hector G. M. Hernandez, Mitko Veleski, Marcelo Brandalero and Michael Huebner|
|15:53-15:56||IP: Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing, Arjun Ramaswami, Tobias Kenter, Thomas Kuhne and Christian Plessl|
|15:56-15:59||IP: Covid4HPC: A Fast and Accurate Solution for Covid Detection in the Cloud using X-Rays, Dimitrios Danopoulos, Christoforos Kachris and Dimitrios Soudris|
|15:59-16:02||IP: A Dataflow Architecture for Real-Time Full-Search Block Motion Estimation, Jesus Barba, Julian Caba, Soledad Escolar, Jose A. T. Heras, Fernando Rincon and Juan Carlos Lopez|
|16:20-17:40||Security (Chair: Maria Mendes Real)|
|16:20-16:45||Increasing Side-Channel Resistance by Netlist Randomization and FPGA-based Reconfiguration, Ali Asghar, Emil Kerimov, Benjamin Hettwer and Daniel Ziener|
|16:45-17:10||Moving Target and Implementation Diversity based Side-Channel Attack Resistant Countermeasures, Nadir Khan, Benjamin Hettwer and Juergen Becker|
|17:10-17:35||Clone-Resistant Secured Booting Based on Unknown Hashing Created in Self-Reconfigurable Platform, Randa Zarrouk, Saleh Mulhem, Weal Adi and Mladen Berekovic|
|17:35-17:38||IP: Providing Tamper-Secure SoC Updates through Reconfigurable Hardware, Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk and Juergen Teich|
|17:40-18:20||Interactive presentations 1|
|Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU, Hector G. M. Hernandez, Mitko Veleski, Marcelo Brandalero and Michael Huebner|
|Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing, Arjun Ramaswami, Tobias Kenter, Thomas Kuhne and Christian Plessl|
|Covid4HPC: A Fast and Accurate Solution for Covid Detection in the Cloud using X-Rays, Dimitrios Danopoulos, Christoforos Kachris and Dimitrios Soudris|
|A Dataflow Architecture for Real-Time Full-Search Block Motion Estimation, Jesus Barba, Julian Caba, Soledad Escolar, Jose A. T. Heras, Fernando Rincon and Juan Carlos Lopez|
|Providing Tamper-Secure SoC Updates through Reconfigurable Hardware, Franz-Josef Streit, Stefan Wildermann, Michael Pschyklenk and Juergen Teich|
|Wednesday 30 June|
|09:00-10:15||Design tools 1 (Chair: Angeliki Kritikakou)|
|09:00-09:25||Supporting On-Chip Dynamic Parallelism for Task-based Hardware Accelerators, Carsten Heinz and Andreas Koch|
|09:25-09:50||Combining Design Space Exploration with Task Scheduling of Moldable Streaming Tasks on Reconfigurable Platforms, Jorg Keller, Sebastian Litzinger and Christoph Kessler|
|09:50-10:15||Task-Based Programming Models for Heterogeneous Recurrent Workloads, Jaume Bosch, Miquel Vidal, Antonio Filgueras, Daniel Jimenez-Gonzalez, Carlos Alvarez, Xavier Martorell and Eduard Ayguade|
|10:35-12:00||Design tools 2 (Chair: Tomasz Kryjak)|
|10:35-11:00||Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA, Johannes Pfau, Peter W. Zaki and Juergen Becker|
|11:00-11:25||Timing Optimization for Virtual FPGA Configurations, Linus Witschen, Tobias Wiersema, Masood R. Nafchi, Arne Bockhorn and Marco Platzner|
|11:25-11:50||Hardware Based Loop Optimization for CGRA Architectures, Chilankamol Sunny, Satyajit Das, Kevin Martin and Philippe Coussy|
|11:50-11:53||IP: Dynamic Spatial Multiplexing on FPGAs with OpenCL, Pascal Jungblut and Dieter Kranzlmuller|
|11:53-11:56||IP: Domain-specific modelling and optimization for graph processing on FPGAs, Mohamed Hassan, Peter Athanas and Yasser Hanafy|
|13:30-15:00||Architecture (Chair: Kevin Martin)|
|13:30-13:55||Multi-Layered NoCs with Adaptive Routing for Mixed Criticality Systems, Nidhi Anantharajaiah, Zhe Zhang and Juergen Becker|
|13:55-14:20||PDU Normalizer Engine for Heterogeneous In-Vehicle Networks in Automotive Gateways, Angela G. Marino, Francesc F. Lluis, Li Ming and Juan M. M. Arostegui|
|14:20-14:45||StreamGrid – an AXI-Stream-compliant Overlay Architecture, Christopher Blochwitz, Leon Philipp, Mladen Berekovic and Thilo Pionteck|
|14:45-14:48||IP: Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications, Ashutosh Dhar, Paul Reckamp, Jinjun Xiong, Wen-Mei Hwu and Deming Chen|
|14:48-14:51||IP: Transparent Near-Memory Computing with a Reconfigurable Processor, Fabian Lesniak, Fabian Kreß and Juergen Becker|
|14:51-14:54||IP: On the Suitability of Read Only Memory for FPGA-based Content-Addressable Memory Emulation, Muhammad Irfan, Kizheppatt Vipin and Ray C. C. Cheung|
|14:54-14:57||IP: FPGA Implementation of Custom Floating-Point Logarithm and Division, Nelson Campos, Slava Chesnokov, Eran Edirisinghe and Alexis Lluis|
|15:00-16:00||Interactive presentations 2|
|Dynamic Spatial Multiplexing on FPGAs with OpenCL, Pascal Jungblut and Dieter Kranzlmuller|
|Domain-specific modelling and optimization for graph processing on FPGAs, Mohamed Hassan, Peter Athanas and Yasser Hanafy|
|Graviton: A Reconfigurable Memory-Compute Fabric for Data Intensive Applications, Ashutosh Dhar, Paul Reckamp, Jinjun Xiong, Wen-Mei Hwu and Deming Chen|
|Transparent Near-Memory Computing with a Reconfigurable Processor, Fabian Lesniak, Fabian Kreß and Juergen Becker|
|On the Suitability of Read Only Memory for FPGA-based Content-Addressable Memory Emulation, Muhammad Irfan, Kizheppatt Vipin and Ray C. C. Cheung|
|FPGA Implementation of Custom Floating-Point Logarithm and Division, Nelson Campos, Slava Chesnokov, Eran Edirisinghe and Alexis Lluisv|